Advanced complementary metal oxide semiconductor (CMOS) devices may increasingly be utilizing metal gate materials instead of the more traditional doped polycrystalline silicon (poly-Si) in order to avoid “poly-Si depletion” and “boron penetration” effects. The selection of a particular metal for a gate material can be guided by a number of considerations, such as, for example, the work function and electrical resistivity desired, the type of gate dielectric with which the gate will be in contact (high-k or other), the thermal budget that the gate metal will be expected to survive, and the existence of a damage-free gate metal deposition process. Though mid-gap metals such as tungsten (W) might be acceptable for both n-type field effect transistors (n-FETs) and p-type field effect transistors (p-FETs) in certain types of CMOS, it is often desirable to use a (high work function) gate metal tailored for p-FETs and another (low work function) gate metal tailored for n-FETs in an approach known as “dual metal/dual work function” CMOS.
In general, metal gates for CMOS devises can comprise one or more layers of a pure metal or alloy, a metal or metal alloy silicide, or a metal-containing conductive oxide or nitride, where at least one of these layers is in contact with the device's gate dielectric. A bilayer metal gate might comprise, for example, a thin bottom “cladding” or “work function-setting” layer (in contact with an underlying gate dielectric) and a thicker upper “fill layer” to provide good conductivity. Ruthenium (Ru) is a gate metal under consideration for p-FETs, either alone, or as a thin cladding layer in combination with a thicker fill layer of W.
Fabrication schemes for metal gate CMOS often utilize a replacement gate process flow in which the gate metal material is made to fill a gap created by the removal of a “dummy gate” (formed earlier in the processing from a “sacrificial place holder” material). An advantage of the replacement gate process is that it allows the metal to be deposited after the dopant activation anneals (often the highest temperature processing steps). A disadvantage often associated with such a process is that most metal deposition techniques cannot fill gaps of the desired dimensions (e.g., lateral <0.1 μm, vertical >0.2 μm) without leaving voids or keyholes.
Existing approaches for gap filling replacement gate structures may have certain disadvantages. For example, in one approach, an in-situ doped poly-Si is deposited into the gap over a metallic cladding layer. The poly-Si is often good at gap filling, but its conductivity is relatively poor and its processing temperature is typically above what can be tolerated by the cladding layer.
In another approach, the gap (which may or may not contain a predeposited metallic cladding layer) is lined with a first layer of thin W formed by chemical vapor deposition (CVD) using a W(CO)6 precursor. Gap filling is then attempted with a second layer of W deposited using a WF6 precursor. Unfortunately, the W from the WF6 precursor often does not fill the gap to the extent desired.
In methods for a “single metal dual/work function” CMOS, a single gate material is deposited over n-FET and p-FET device areas and then modified so that it has an n-FET-appropriate work function in n-FET device areas and a p-FET-appropriate work function in p-FET device areas. For example, Misra, et al., “Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS”, IEEE Electron Device Letters 23 354 (2002), have deposited a ruthenium-tantalum (Ru—Ta) alloy with an n-FET work function over n-FET and p-FET device areas and then converted the Ru—Ta alloy into an Ru-rich Ru—Ta alloy with a p-FET work function (in the p-FET device areas) by deposition and annealing of additional Ru. See also, Zhong, et al., “Properties of Ru—Ta Alloys as Gate Electrodes for NMOS and PMOS Silicon Devices”, IDEM 01 467 (2001). The fabrication of a patterned Ru layer for this additional Ru could be simplified if the Ru could be selectively deposited only in the p-FET device areas.
The approaches and methods described in detail below may overcome at least one of the shortcomings discussed above.